A 300 mm wafer has 2.25 times the area of a 200 mm wafer. Infineon says it gives 2.3 times the chips. That extra 0.05 is not a typo. It is geometry.
On November 9, 2026, Infineon said it had processed 300 mm silicon carbide (SiC) wafers into functional power devices at its Villach, Austria fab, using existing silicon manufacturing equipment, and showed the wafer at electronica in Munich (November 10–13). It also reported feasibility of its Cold Split wafer-separation process at 300 mm in Dresden (Infineon press release).
What Infineon did not publish: yields, device ratings, electrical test data or a volume ramp date. 200 mm remains its production roadmap (Electronic Design). So the useful question is not "is SiC now cheap?" but "what has to be true for a 300 mm SiC wafer to pay off?" Here is the math.
1. 300 mm SiC Wafer Area vs. Die Count: Why 2.25× Becomes 2.3×
Area scales with diameter squared. Die count scales a little faster, because the wasted partial dies at the edge grow only with the circumference.
Gross dies per wafer (DPW):
DPW = π·D² / (4·S) − π·D / √(2·S)
D = usable diameter, S = die area
Example: S = 25 mm² (5 × 5 mm die), 3 mm edge exclusion
200 mm: D = 194 → DPW ≈ 1,182 − 86 ≈ 1,096
300 mm: D = 294 → DPW ≈ 2,716 − 131 ≈ 2,585
Ratio ≈ 2.36
With a mid-size power MOSFET die, the ratio lands at about 2.36, right next to Infineon's 2.3× claim. The bigger the die, the more the edge term matters, and the more a large wafer helps. The die size and edge exclusion here are illustrative, not Infineon data.
2. SiC Defect Density and Yield: The Poisson Model
Gross dies are not good dies. SiC crystals carry defects such as micropipes, threading dislocations and basal-plane dislocations, and a single killer defect can scrap a die. The simplest yield model is Poisson:
A = die area (cm²), D₀ = killer defect density (cm⁻²)
A = 0.25 cm² (example):
D₀ = 0.2 → Y ≈ 95.1%
D₀ = 0.5 → Y ≈ 88.2%
D₀ = 1.0 → Y ≈ 77.9%
A larger wafer does not change device physics. It only changes how many shots you get per pass through the fab. If the first 300 mm substrates come with a higher defect density than mature 200 mm material, part of the 2.36× gain disappears before a single die is packaged. For large traction-inverter dies, the penalty grows exponentially with area.
3. Cost per Good Die: The Break-Even Wafer Cost Formula
Combine die count and yield into one number:
300 mm wins when:
C_300 / C_200 < (DPW_300 / DPW_200) × (Y_300 / Y_200)
Example: Y_200 = 95.1% (D₀ 0.2), Y_300 = 88.2% (D₀ 0.5)
Break-even cost ratio = 2.36 × 0.882 / 0.951 ≈ 2.19
Under these example numbers, a processed 300 mm SiC wafer must cost less than about 2.2× a 200 mm wafer to lower cost per good die. That is why Infineon's mention of reusing existing silicon equipment matters: tool depreciation spread over 2.36× more dies per wafer pass is where the savings come from. The substrate itself is the open question, since SiC boules grow slowly and 300 mm substrates are not yet available in commercial quantities (Credence Research). For why SiC is worth this trouble in 800 V EVs, see our video From 400V to 800V: The Silicon Carbide Revolution.
4. Cold Split vs. Wire Saw: Wafers per SiC Boule
The second announcement attacks substrate cost directly. A diamond wire saw turns part of every slice into kerf dust. Cold Split, developed by Siltectra (acquired by Infineon in 2018), uses a laser to create a subsurface damage plane, then uses stress to split the wafer off with far less material lost (Electronic Design).
Example: L = 30 mm, t_wafer = 350 µm, t_grind = 150 µm
Wire saw, kerf 180 µm: 30,000 / 680 ≈ 44 wafers
Split, loss 80 µm: 30,000 / 580 ≈ 51 wafers
Gain ≈ +16% wafers from the same crystal
All these thicknesses are illustrative, and Infineon has not published material-recovery figures at 300 mm. But the structure is clear: once grinding and polishing dominate the loss budget, cutting kerf is the next lever. Multiply a 2.36× die-count gain by a mid-teens wafer-per-boule gain and you see why the industry wants both at once. Our earlier post on the 2300 V SiC module for 1500 V grids shows where those dies end up.
- Infineon's actual 300 mm SiC yield, defect density, device ratings and ramp date. None has been disclosed.
- The die size and edge exclusion behind Infineon's 2.3× claim. Our 5 × 5 mm example is illustrative.
- Real kerf, grinding and Cold Split loss figures at 300 mm. The boule and thickness values above are examples, not measurements.
- Processed-wafer cost ratio of 300 mm vs. 200 mm SiC. The 2.2× break-even depends entirely on the example yields.
The Engineering Takeaway on 300 mm SiC Wafers
- 2.3× is geometry, not yield. Die count grows slightly faster than area because edge loss scales with circumference.
- Defect density decides the win. Poisson yield punishes large dies exponentially, so early 300 mm substrates must match mature 200 mm quality.
- Watch the break-even ratio. In our example, 300 mm pays off only if the processed wafer costs under about 2.2× a 200 mm wafer.
- Substrate cost is the real bottleneck. Cold Split targets wafers per boule, the input that larger diameter alone cannot fix.
Sources: Infineon (Nov 9, 2026); Electronic Design; Credence Research. Calculations by The Engineering Core using the illustrative assumptions stated above.
