At 12 volts, 24 kilowatts is 2,000 amps. That number alone explains why every milliohm between the converter and the GPU still matters—and why Navitas just showed another way to get there from an 800 VDC rack bus.
At the 2026 Open Compute Project Global Summit (October 12–15, San Jose), Navitas Semiconductor announced a 24 kW, 800 VDC-to-12 VDC power delivery board (PDB) developed with NVIDIA for the MGX ecosystem. It is a single-stage GaNFast design meant to sit on the compute motherboard, feed the voltage regulator module (VRM) directly, and skip the usual 50 V-to-12 V intermediate bus converter (IBC). Coverage and specs appear in Power Electronics News (Oct 15, 2026) and Semiconductor Today (Oct 13, 2026).
This is a different board from the earlier Navitas–Microchip 800 V-to-6 V reference design. Same 800 VDC rack story, different intermediate rail, different partner, different current budget. Below: the engineering math.
Key point: Going 800 V → 12 V in one stage does not eliminate high current—it just moves the remaining step-down into the VRM. At 24 kW / 12 V you still push about 2,000 A on the board. The win is fewer conversion stages, denser copper paths, and a shorter path from bus to GPU.
1. What was announced (and how it differs from 800 V → 6 V)
According to Power Electronics News and Semiconductor Today, the PDB is specified as:
- 24 kW output capacity for an entire compute tray
- Target full-load efficiency of 97%
- Power density exceeding 2,000 W/in³
- NVIDIA form factor 400 mm × 60 mm, integrable onto the compute motherboard next to the xPUs
- Primary side: 16 × NV6034 GaNFast FETs (650 V, 18 mΩ) in a stacked half-bridge, dual-cooled 8 mm × 8 mm DFN packages
- Architecture: single-stage 800 VDC → 12 VDC, eliminating the conventional 50 V → 12 V IBC; 12 V feeds the VRM
Navitas already had a 20 kW, 800 V-to-6 V PDB with NVIDIA. The new board extends that portfolio so designers can pick a 12 V or 6 V intermediate rail to match their VRM strategy (Semiconductor Today). Same family, different voltage story.
2. The current math: 24 kW looks tame at 800 V and brutal at 12 V
Power is voltage times current. For the same 24 kW tray:
I_in ≈ P / (η × V_in) = 24,000 / (0.97 × 800) ≈ 30.9 A
I_out = P / V_out = 24,000 / 12 = 2,000 A
(Input current uses the 97% target so the board draws a little more than P/V from the bus. Output current is P/V if 24 kW is the delivered power—confirm whether the published 24 kW is input or output; see the to-verify box.)
Conduction loss scales with I²R. Put an illustrative 0.1 mΩ interconnect in each path:
P_loss,800V = (30.9)² × 0.0001 ≈ 0.10 W
P_loss,12V = (2,000)² × 0.0001 = 400 W
Same scrap of copper, four-thousand-times different heat. That is why the PDB form factor puts conversion on the motherboard next to the GPUs instead of shipping 2,000 A across a shelf. Compare with the 6 V story: at 20 kW / 6 V you need about 3,333 A. Choosing 12 V halves that current for a similar tray power—at the cost of one more VRM conversion stage before the core rails.
3. Why kill the 50 V IBC: stages, losses, and board real estate
A conventional tray path looks like: 800 V (or 48/50 V shelf) → IBC → 12 V → VRM → core. Each stage burns a few percent and eats PCB area. Navitas' claim for this board is a single stage from 800 VDC straight to 12 VDC, so the IBC disappears and the VRM becomes the only remaining low-voltage converter (Power Electronics News).
A back-of-envelope cascade check helps frame the target. If a legacy two-stage path ran at 97% × 97% ≈ 94.1% end-to-end, a single 97% stage saves about three points of conversion loss before the VRM. That is illustrative stage efficiency, not a measured system comparison—real IBC and PDB curves vary with load and temperature. The density claim is the complementary half: more than 2,000 W/in³ on a 400 × 60 mm outline means most of the tray volume stays available for compute, not magnetics.
Sanity check on density (my calculation, not theirs). If we assume a 6 mm board thickness like other recent thin PDBs in this class, volume ≈ 40 × 6 × 0.6 cm = 144 cm³ ≈ 8.8 in³. Then 24 kW / 8.8 in³ ≈ 2,730 W/in³—above the "exceeding 2,000 W/in³" floor. Thickness and what volume is counted will move that number; treat it as a consistency check, not a published dim.
4. GaN primary: 16 FETs, stacked half-bridge, and the heat bill
The primary uses 16 NV6034 devices at 650 V / 18 mΩ in a stacked half-bridge with dual-cooled DFN 8×8 packages (Semiconductor Today). Stacking is the usual trick for an 800 V bus on 650 V parts: each half-bridge sees roughly half the bus, leaving headroom for ringing—same idea that shows up in ISOP and series-stacked GaN designs elsewhere.
At 97% of 24 kW, the board itself must reject about:
P_loss ≈ 0.03 × 24 kW = 720 W
That heat has to leave through dual-side cooling into whatever cold plate or heat path the motherboard provides. Dual-cooled packages help by presenting two thermal faces per FET, but 720 W on a 400 × 60 mm outline is still a packaging and liquid-cooling problem, not a "small heatsink" problem. Expect the real design limit to be thermal and transient response under GPU load steps, not just the DC efficiency number.
To verify:
- Whether the published 24 kW is delivered output power or input power, and the exact load point where 97% is measured (full-load curve not in the coverage cited).
- Board thickness and the volume basis for ">2,000 W/in³"—my 6 mm assumption is illustrative.
- Stacked half-bridge balancing, transformer/rectifier details, and transient response to GPU current steps—not described in the press coverage.
- Production qualification status: this is an announced PDB for MGX Wall display at OCP, not a shipping shelf PSU.
Bottom line
Navitas and NVIDIA's 24 kW board is the 12 V sibling of the 800 V rack story: single-stage GaN conversion, motherboard form factor, and a deliberate choice to stop at 12 V so existing VRM ecosystems can finish the job. Run the current math first—~31 A in, ~2,000 A out—then ask how many conversion stages and how many milliohms still sit between that rail and the silicon.
Sources: Power Electronics News (Oct 15, 2026) · Semiconductor Today (Oct 13, 2026) · EEJournal / Navitas announcement
