Hook: Most power-electronics roadmaps still start with the same question: which die wins—Si, SiC, or GaN? On September 16, 2026, onsemi answered a different question: what if the package—not the die—is the real density ceiling?
Its new Embedded Power Platform (EPP) treats the silicon wafer itself as the foundation of the package. FETs, drivers, and controllers—including mixed Si / SiC / GaN dies—can be embedded and interconnected at wafer level. onsemi claims this co-designed electrical–mechanical–thermal stack can deliver up to 3–5× higher power density versus conventional approaches, depending on the application (onsemi / GlobeNewswire, Sept 16, 2026). Sampling with strategic customers is expected in 2026 (same source).
Key takeaway: This is not another “better MOSFET” launch. It is an argument that DBC ceramics, wire bonds, and mold compound have become the bottleneck for AI racks, EV inverters, and compact industrial drives.
What happened
In the press release, CEO Hassane El-Khoury framed the shift bluntly: for decades the semiconductor and the package were treated as separate technologies; EPP makes the silicon itself part of the system architecture. Mechanically, that means:
- Use a standard 12-inch silicon wafer process flow as the packaging substrate.
- Embed multiple dies (power FETs plus gate drivers / controllers) into that wafer-level structure.
- Interconnect them with wafer-level redistribution instead of classical wire bonds.
- Co-optimize electrical parasitics, mechanical stress, and heat extraction from day one, rather than stacking three sequential design teams.
onsemi also named Subaru as an early engagement partner for evaluating electrified-vehicle architectures, with early access to engineering samples, simulation models, and technical support (same GlobeNewswire release). That matters: packaging platforms only become real when an OEM is willing to requalify a powertrain inverter around them.
Independent coverage of the same launch notes that EPP aims to displace traditional power-module stacks built from DBC isolation substrates, wire bonds, and mold compound, and that silicon’s thermal conductivity (roughly 130–150 W/m·K) is being positioned as a better heat path than mold compound—figures reported in trade press summarizing onsemi interviews (Power Electronics News; verify before cite-as-fact if you need absolute values).
Engineering mechanism: why the package was eating your density budget
A conventional high-power module looks “solved” on a slide: SiC dies on DBC, wire-bonded, molded, bolted to a cold plate. In the lab, three failure modes keep showing up:
- 1) Loop inductance
Wire bonds and long lead frames add nanohenries that look harmless at 10 kHz and ugly at 50–100+ kHz. Voltage overshoot, EMI, and forced soft-switching deratings follow. - 2) Thermal stack mismatch
Heat must cross die attach → ceramic → baseplate → TIM → cold plate. Every interface is a temperature rise you paid for with copper and fans. - 3) Sequential co-design debt
Power EE picks the FET; packaging locks the footprint; thermal CFD arrives last and asks for a larger heatsink. Late changes are expensive.
EPP’s bet is to collapse those three loops. If the wafer is the package:
- Interconnect lengths shrink toward RDL-scale geometries → lower parasitic inductance → room for higher switching frequency and tighter device control (onsemi’s stated intent).
- Heat can spread across the full silicon footprint rather than through a narrow mold-compound chimney (onsemi positioning for AI power stages).
- A half-bridge + driver + controller can be co-simulated as one object, cutting the classic “electrical OK / thermal fail / mechanical crack” iteration spiral. onsemi markets development cycles that can compress to as little as four months on this platform (GlobeNewswire claim—treat as vendor roadmap, not an industry average).
Vendor numbers (directional, not fleet-validated):
- EV traction class: up to 4× power density and ~15% lower losses vs conventional approaches (same release).
- AI racks: packaging density becomes a tokens-per-rack problem as much as joules-per-switch—conversion hardware steals board area and cooling from compute.
The misconception worth killing
Misconception: “Buy a better wide-bandgap die and density will follow.”
Reality check: Once FET conduction and switching losses drop, the next watts and cubic centimeters are often lost in bond-wire inductance, ceramic thermal resistance, driver–FET separation, and multi-die layouts that cannot share a common thermal plane.
Heterogeneous embedding (Si control + SiC/GaN power in one wafer-level object) is onsemi’s answer to that systems gap. It is closer to advanced logic packaging thinking—RDL, multi-die, co-design—than to classic discrete TO-247 shopping.
What EPP does not automatically solve:
- Isolation and creepage at 400 V / 800 V still need careful design—embedding dies does not delete dielectric physics.
- Qualification burden (AEC-Q, power-cycling, humidity, shock) moves onto a new package class; Subaru is evaluation, not mass production.
- Supply-chain and yield for embedding SiC/GaN into 12-inch silicon flows are non-trivial.
- “3–5× density” and “15% lower losses” remain application-dependent vendor claims until independent benchmarks land.
Takeaway judgment
If you design AI power stages, EV inverters, or compact industrial motor drives in 2026, the interesting question is no longer only “SiC or GaN?” It is:
Are you still paying a packaging tax that cancels the wide-bandgap advantage?
onsemi’s EPP is a credible industry signal that power modules are migrating toward wafer-level, multi-die, co-optimized systems—the same direction logic packaging took years ago. Watch three checkpoints before you redesign a platform around it:
- Independent thermal and parasitic measurements on shipping samples (not only press-kit slides).
- Automotive and industrial qualification depth beyond early-access partners.
- Whether a common EPP-based half-bridge really reuses cleanly across power classes without hidden derating.
Die technology still matters. But if the September 16 announcement holds up in silicon, the next density leap will be won in the package—because the package finally is the silicon.
Related: @TheEngineeringCore-v · @Vkinng · vkinngworld.blogspot.com
Sources: onsemi / GlobeNewswire (2026-09-16); Power Electronics News coverage of EPP. Vendor performance figures marked as claims—spot-check before citing as measured results.
—— The Engineering Core
